• Publications
  • Influence
Design and analysis of ring oscillator based Design-for-Trust technique
TLDR
A non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors, and is applicable to both ASICs and FPGA implementations.
BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks
TLDR
This work proposes a host based DDoS detection framework called BRAIN: BehavioR based Adaptive Intrusion detection in Networks, which combines network statistics and modeled application behavior to detect DDoS attacks using machine learning.
Fingerprinting Field Programmable Gate Arrays
TLDR
This work confirmed FPGA fingerprinting on 56 Xilinx Artix-7 FPGAs and presented an approach to fingerprint FPG as by leveraging process variations and spatial correlations.
Blue team red team approach to hardware trust assessment
TLDR
By following a red team blue team approach, two trojan detection techniques namely, path delay measurement and ring oscillator frequency monitoring, were validated in the Embedded Systems Challenge (ESC) 2010.
Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems
TLDR
The proposed Deep Packet Field Extraction Engine (DPFEE) is a content-aware, grammar-based, Layer 7 programmable field extraction engine for text-based protocols that can be easily scaled beyond 300 Gbps.
FPGA Trust Zone: Incorporating trust and reliability into FPGA designs
TLDR
FTZ helps identify and partition the FPGA into areas that are devoid of anomalies and thus, assists to run designs securely and reliably even in an anomaly-infected FPGAs.
DPFEE: A High Performance Scalable Pre-Processor for Network Security Systems
TLDR
This work proposes a novel Deep Packet Field Extraction Engine (DPFEE) for application layer field extraction to hardware that achieves 3.14X higher bandwidth, 1020X lower latency, and 106X lower power consumption, when compared with 200 parallel streams of GPU accelerated preprocessor.
Intra-die process variation aware anomaly detection in FPGAs
TLDR
A new non-destructive method to determine the presence of anomalies such as Hardware Trojans in physical VLSI layer of FPGA, especially in configurable logic blocks and switch blocks, which does not require a golden chip to compare with a chip under test and can be performed without expensive testing equipment.
Hardware Trojan Attacks in FPGA and Protection Approaches
TLDR
This book chapter explains how attackers can insert Trojans into FPGAs, and presents a Trojan taxonomy that is tailored to FPGA supply chain.
TAINT: Tool for Automated INsertion of Trojans
TLDR
A Tool for Automated Insertion of Trojans (TAINT), which can evaluate FPGA based designs against known and unknown attacks, and automate Trojan Testing.
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