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Architecture and CAD for Deep-Submicron FPGAS
From the Publisher: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issuesExpand
VPR: A new packing, placement and routing tool for FPGA research
We describe the capabilities of and algorithms used in a ne w FPGA CAD tool, Versatile Place and Route (VPR). Expand
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. Expand
Timing-driven placement for FPGAs
We introduce a new Simulated Annealing-based timing-driven placement algorithm for FPGAs that is able to increase the post-place-and-route speed of 20 MCNC benchmark circuits by 42%. Expand
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
In 1999, most commercial FPGA, like the Altera Flex and Xilinx Virtex FPGAs already had cluster-based logic blocks. Expand
COFFE: Fully-automated transistor sizing for FPGAs
In this paper, we present COFFE (Circuit Optimization For FPGA Exploration), a new fully-automated transistor sizing tool for FPGAs. Expand
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II logic and routing architecture. Expand
FPGA routing architecture: segmentation and buffering to optimize speed and density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transistor and tri-state buffer routing switches. Expand
Titan: Enabling large and complex benchmarks in academic CAD
We present Titan, a hybrid CAD flow that addresses these issues. Expand
Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD
Benchmarks play a key role in Field-Programmable Gate Array (FPGA) architecture and CAD research, enabling the quantitative comparison of tools and architectures; however, most current FPGA benchmarks are both small and simple. Expand