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- Pradip Mandal, V. Visvanathan
- IEEE Trans. on CAD of Integrated Circuits and…
- 2001

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the… (More)

- Linda S. Milor, V. Visvanathan
- IEEE Trans. on CAD of Integrated Circuits and…
- 1989

- P. Sadayappan, V. Visvanathan
- IEEE Trans. Computers
- 1988

- Dinesh Somasekhar, V. Visvanathan
- VLSI Design
- 1993

cuitry are the key features of this design. Simulation studies indicate that the multiplier dissipates 540 mW at 230 MHz. The multiplier cell has 5176 transistors, with dimensions of 1.5 mm x 1.4 mm. This multiplier satisfies the need for very-high throughput multiplier cores required in DSp architectures. plications may be delivered from the multiplier… (More)

- S. Ramanathan, V. Visvanathan
- Integration
- 1999

- Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan
- 1993 International Conference on Parallel…
- 1993

The concept of supernodes has been widely used in the design of algorithms for the solution of sparse linear systems of equations. This paper discusses the use of supernodes in the design of algorithms for sparse Cholesky factorization on distributed-memory multiprocessors. A new algorithm that is communication efficient, has good load balance, and benefits… (More)

- S. Ramanathan, V. Visvanathan, S. K. Nandy
- Integration
- 1999

- V. Visvanathan, Linda S. Milor
- Symposium on Computational Geometry
- 1986

An efficient algorithm to determine the image of a parallelepiped under a linear transformation is presented. The work was motivated by certain problems in the testing of analog integrated circuits. The method is based on specifying the boundary hyperplanes that define the image polytope and is of polynomial complexity in <italic>n</italic> (the dimension… (More)

- Bishnu Prasad Das, Bharadwaj S. Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan
- 2008 IEEE Custom Integrated Circuits Conference
- 2008

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in… (More)

- S. Ramanathan, V. Visvanathan
- VLSI Design
- 1996

Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. T h e… (More)