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With increasing use of low cost wire-bond packages for mobile devices, excessive dynamic IR-drop may cause tests to fail on the tester. Identifying and debugging such scan test failures is a very complex and effort-intensive process. A better solution is to generate correct-by-construction "power-safe" patterns. Moreover, with glitch power contributing to a(More)
This paper proposes a new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA. The proposed testing technique detects all possible routing errors including bridging faults, and requires a single configuration of only the LUTs of the FPGA. Any routing error(More)
In this paper, we propose a novel <i>temporal redundancy</i> based encoding technique for delay and peak power minimization. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks for 90<i>nm</i> and 65<i>nm</i> technologies. The experimental results show that our approach is very effective in reducing the peak power. From the delay(More)