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Introduction: Charge trapping (CT) memory cells are a promising candidate to replace floating gate (FG) cells in NAND applications around the 30 nm technology node [1]. Difficulties to place the control gate (CG) plug in between adjacent FG cells cause serious problems to provide a sufficiently high gate coupling ratio. As a result the program and erase(More)
With technology scaling of embedded nonvolatile memories, voltage scaling below 12 V is a primary goal to maintain the area efficiency of the memory module. The SONOS technology shows promise as a technology for present and future low voltage memory cells. This paper examines the physics of scaled SONOS gate dielectrics in relation to reducing the(More)
This letter investigates a new select device disturb phenomenon in TANOS NAND flash memories. Since NAND string select devices contain the same charge trap (CT) stack as the memory cells, they are, in principle, programmable. We observe a select threshold voltage increase during cycling of the cell array. This disturb is caused by electron injection from(More)
The polarity-dependent device degradation during AC stress of polysicilicon-oxide-nitride-oxide-silicon (SONOS) transistor poses considerable reliability challenges for scaled SONOS gate oxide thicknesses. However, the mechanism responsible for the endurance degradation has been scarcely studied so far. Especially electrons injected from the gate are(More)
Program disturb may ultimately limit the scalability of modern NAND flash memory technologies and is typically most serious for the memory cells neighboring the string select transistors. The feasibility, accuracy, and predictive capability of a new advanced physical simulation model for the program disturb in NAND flash memories is demonstrated by means of(More)
On TANOS (Tantalum Alumina Nitride Oxide Silicon) charge trap cells an anomalous effect is observed during cell erase operation. Different TANOS cell architectures are investigated including an encapsulation liner of different thickness. Especially on cells fabricated without such a liner an unintended programming is observed and characterized in detail. A(More)
Random Telegraph Noise (RTN) characterization was performed on charge-trap-based TANOS memory cells. The analysis results of cycle stress dependence and cell size scaling are discussed based on single cell measurements. Comparing charge-trap and floating-gate memory technologies different behavior for RTN was obtained. On charge-trap cells a threshold(More)
In our work we present statistical methods and new memory array analysis approaches for decomposition and assessment of contributors to the V<sub>th</sub> distribution widening. There, cell threshold voltage characteristics along bitlines and wordlines are considered as well as hidden systematic effects by convolutional analysis. Based on investigations on(More)