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This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the… (More)
In this paper, we present an original test synthesis approach for data paths of VLIW based processors. Our approach is a library-based method, in which together with components, canned tests are stored. The aim of our approach is to synthesize data paths and corresponding test sets in parallel.
In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy,… (More)