Uwe Zschenderlein

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In this paper the residual stress in single-crystalline Si around W-filled TSVs was determined experimentally by three methods with high spatial resolution and compared to one another. In contrast to Cu as TSV filler, W has the potential advantage of a lower CTE mismatch to Si resulting in lower thermally induced stress at the TSV-interface. As test layout(More)
Flip chip interconnects purely made out of Cu, so-called all-Cu interconnects, have the potential to overcome the present current capacity limit of state-of-the-art solder based interconnects, while meeting the demand for ever decreasing interconnect pitches. Parasitic effects in solder based interconnects, caused by interdiffusion of various metals, are(More)
The cost and the package size driven size reduction of semiconductors lead to much higher heat generation. Also the use of new high power technologies on the basis of SiC produces is a need for high conductivity of the interconnect materials. Therefore the requirements for mechanical, thermal and electrical properties of interconnect materials increase(More)
To satisfy the increasing need in today's industry for high performance, more complex chips are being designed. These chips, when integrated in 3D packages, have a high energy density and require new and innovative cooling strategies as many of them are designed as flip-chip assemblies, usually requiring back-side cooling. Classical underfills currently(More)
Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that(More)
Three different experimental methods have been used to determine mechanical stresses in silicon nearby tungsten TSVs - HR-XRD performed at a synchrotron beamline, microRaman spectroscopy and stress relief techniques put into effect by FIB ion milling. All methods possess, to a different extend, high spatial resolution capabilities. However they differ in(More)
A dual-side cooling topology is proposed that is achieved by embedding a power insert into the organic substrate of a chip or chip stack. The power insert consists of vertical copper lamellas supporting lateral current feed in addition to vertical heat dissipation at minimal electrical and thermal gradients. The lateral current feed capability is key to(More)
Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical(More)
This paper addresses both, the thermal and the thermo-mechanical performance of percolating thermal underfill applied flip-chip packages. We present a thermal test platform in flip-chip package design allowing the thermal conductivity of any underfill to be measured at package scale. We give details about design technology and current fabrication status. We(More)