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| Recently, it has been shown in [1] and [2] that in order to verify the correct timing of a manufactured circuit not all of its paths need to be considered for delay testing. In this paper, a theory is developed which puts the work of these papers into a common framework, thus allowing for a better understanding of their relation. In addition, we consider… (More)

The eeectiveness of residue code checking for on-line error detection in parallel two's complement multipliers has up to now only been evaluated experimentally for few archi-tectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the… (More)

Recently, Pomeranz and Reddy [7], presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at… (More)

- Uwe Sparmann
- VTS
- 1993

| It has been shown earlier that, if we restrict to unate gate network (UGN) realizations, there exist universal test sets for boolean functions. Such a test set only depends on the function f , and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper we prove that these universal test… (More)

We consider delay testing of a speciic class of logic circuits, the so calledùnate gate networks (UGNs)', which are of importance for the realization of dynamic CMOS logic and in the eld of on-line error detection. It has been shown earlier, that UGNs can be tested completely for delay faults withùniversal' test sets. This result even holds for designs… (More)

- Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor +3 others
- EURO-DAC
- 1990

The two most important frontend components of the VLSI design system CADIC are presented. The first one allows graphical specification of recursively defined circuits. The other one allows the designer to navigate across the synthesized layout following the hierarchical specification to check e.g. CADIC's hierarchical optimizations or to control the outcome… (More)

We present several methods which accelerate fault simulation for combinational circuits using parallel pattern evaluation. The methods are based on an extensive structure analysis of the considered circuit. On the one hand the developed methods aim at a reduction of fanout stems for which the fault simulation has to be performed and on the other hand at a… (More)