Usha Mehta

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Testability measures are controllability and observability. Controllability guides the test generation algorithms while setting a value to primary input (PI) in line justification problem. When more than one path are available for error propagation Observability finds which path is to be select. This paper describes controllability functions (CC0, CC1) and(More)
QCA (Quantum-dot Cellular Automata) is the most capable future nanotechnology for computing. Defects are most likely to occur in QCA devices due to the nanoscale Faults caused by these defects must be analyzed. This paper implement the QCA combinational circuit, half adder for which fault analysis is carried out. This paper presents the fault analysis of(More)
Digital to analog converter is widely used mixed-signal circuit. Testing of analog and mixed signals faces lots of challenges due to the wide range of circuits and unavailability of one appropriate fault model. SAF (stuck_at_Fault), Stuck_open and stuck_short fault model at transistor level is used in this paper. Further these fault models are used to(More)
System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today's integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That's why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge about their(More)
CMOS technology has achieved the device dimension in the nanometer range. Beyond this CMOS technology is the QCA (Quantum-dot Cellular Automata). Due to nanoscale defects may occur in this technology so in the consequences of it the faults will occur. This paper presents the defect analysis of QCA basic devices like Majority Voter (MV), inverter. The defect(More)
In the current scenario of IP core based SoC, to reduce the test time and test cost, the test data is preprocessed and compressed heavily. This compressed test data are transferred from Automatic Test Equipment (ATE) to chip under test through a serial communication link and will be decompressed on-chip before applying to actual DUT. If there is a problem(More)
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is(More)
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