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In this paper, we show how a multiprocessor can be physically detached from its main memory using commercially available secondary cache controllers and high-speed ber optic links organized as a star network. The implementation connects up to eight Motorola 88110 processors to a single memory controller/directory cache. The memory access latency in this(More)
BACKGROUND The effects of freezing-thawing cycles on intramedullary bone-implant interfaces have been studied in a rat model in mechanical pull-out tests. IMPLANTS: Twenty TiAl6V4 rods (Ø 0.8 mm, length 10 mm) implanted in rat tibiae METHODS 10 rats underwent bilateral tibial implantation of titanium rods. At eight weeks, the animals were sacrificed and(More)
High performance multiprocessors generally require a very complex underlying hardware. This applies notably to shared memory systems, where the communication grain is fine and hence low latencies are critical. We describe the prototype of a multiprocessor network which is based on low-cost standard technology. We point out the main difficulties encountered(More)
Allegro: un simulateur dirig e par ex ecution eecace R esum e Le temps requis pour le cycle de d eveloppement mat eriel/logiciel a diminu e en m^ eme temps que le co^ ut de d eveloppement (i.e. erreurs) a augment e. Les m ethodes analytiques ne sont pas suusamment g en erales pour simuler tous les aspects du fonctionnement d'un multiprocesseur. La(More)
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