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We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator… (More)

For point sets in the rectilinear plane we consider the following five measures of the interconnect length and prove bounds on the worst-case ratio: minimum Steiner tree, minimum star, clique, minimum spanning tree, and bounding box. In particular, we prove that for any set of n points: (n − 1) times the shortest Steiner tree is less or equal to the clique… (More)

VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (<i>global placement</i>). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (<i>detailed placement</i> or… (More)

We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the total quadratic netlength, we partition the chip area into regions and assign the circuits to them (meeting capacity constraints) such that the placement is changed as little as… (More)

We present a new approach to VLSI placement legalization. Based on a minimum-cost flow algorithm that iteratively augments flows along paths, our algorithm ensures that only augmentations are considered that can be realized exactly by cell movements. Hence, the method avoids realization problems which are inherent to previous flow-based legalization… (More)