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VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (<i>global placement</i>). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (<i>detailed placement</i> or(More)
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the total quadratic netlength, we partition the chip area into regions and assign the circuits to them (meeting capacity constraints) such that the placement is changed as little as(More)