Udit Narula

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TSV and micro-Solder bump are key interconnects for 2.5D and 3D Integrated circuit (IC) chips, and being part of interconnects for IC, their Electromigration reliability must be assessed. However, their resistances are much smaller than that of interconnect lines in IC, and this renders difficulty in having accurate resistance monitoring of TSV and(More)
Growth mechanism for synthesizing PVD based Graphene using Amorphous Carbon, catalyzed by Copper is investigated in this work. Different experiments with respect to Amorphous Carbon film thickness, annealing time and temperature are performed for the investigation. Copper film stress and its effect on hydrogen diffusion through the film grain boundaries are(More)
A systematic method to identify key factors that control the synthesis of Physical Vapor Deposition (PVD)-based graphene on copper is necessary for engineering graphene growth. The statistical design-of-experiments method is employed and demonstrated in this work in order to fulfill the necessity. Full-factorial design-of-experiments are performed to(More)
In the present paper our objective is to emphasize the importance of Vedic Mathematics for digital applications. Ancient vedic mathematics not only facilitate the complex mathematical operations but also useful for logical applications. In the present work we are using the concept of Urdhva-tiryakbyham, i.e., vertically and crosswise multiplication and it's(More)
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