Udayan Mallik

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A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an(More)
We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition,(More)
An integrated array of 2,400 spiking silicon neurons, with reconfigurable synaptic connectivity and adjustable neural spike-based dynamics, is presented. At the system level, the chip serves as an address-event transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven bus. Internally, every cell implements a spiking(More)
We present an architecture for processing spike-based sensory information in real-time. The system is based on a re-configurable silicon array of general-purpose integrate-and-fire neurons (as opposed to application-specific circuits), which can emulate arbitrary cortical networks. A combined retinal/cortical network has been designed and tested with a(More)
Covert, low-power and low-bandwidth sensor networks for intelligent surveillance require imaging front-ends that make rudimentary decisions to perform or facilitate data compression. Typically, this front-end is composed of a standard Active Pixel Sensor (APS), an ADC and additional digital logic for image processing and communication control. As is(More)
We have constructed a system that uses an array of 9,600 spiking silicon neurons, a fast microcontroller, and digital memory, to implement a reconfigurable network of integrate-and-fire neurons. The system is designed for rapid prototyping of spiking neural networks that require high-throughput communication with external address-event hardware. Arbitrary(More)
An array of 90 90 active pixel sensors (APS) with pixel-level embedded differencing and comparison is presented. The nMOS-only 6T 2C 25 m 25 m pixel provides both analog readout of pixel intensity and a digital flag indicating temporal change at variable thresholds. Computation is performed through a pixel-level capacitively coupled comparator which also(More)
We have implemented a foveated vision system that uses an 80 × 60 address-event neuromorphic image sensor and varies its effective spatial acuity throughout the visual field to use bandwidth more efficiently. Low resolution pixels are created by pooling spikes from neighboring photoreceptors using overlapping Gaussian kernels. The pooling is effected by(More)
We have constructed a system that uses an array of 9,600 spiking silicon neurons, a fast microcontroller, and digital memory, to implement a reconfigurable network of integrate-and-fire neurons. The system is designed for rapid prototyping of spiking neural networks that require high-throughput communication with external address-event hardware. Arbitrary(More)