Uday Panwar

  • Citations Per Year
Learn More
Power consumption has become hurdle for recent IC design as technology scale down below 45nm. Aggressive nanoscaling of MOS transistor in process technology has advanced in chip density, but to achieve high performance and lower power consumption by continues scaling results in shorter channel effect and Lowering of Drain Induced Barrier Lowering (DIBL). To(More)
Power dissipation is major drawback in the digital sequential circuit design of low power electronic devices. Clock signal is one input which is common for all the sequential circuits. The clock signal has major power dissipation at high frequencies. The clock gating technique can be implemented at architectural level to reduce the power dissipation at(More)
In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Leakage power decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder(More)
Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems(More)
As technology scales down below 65nm there is a rapid growth in semiconductor industries; reduction in transistor size leads to exponential increase in power consumption in DSM technology. The major concerns of VLSI designers are to develop a circuit which is having high performance with minimal size earlier. The fast growth in portable computing and(More)
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in(More)
Leakage current in CMOS circuits can be controlled at the circuit level and at the device level as well. One of the circuit level control techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be reduced in the sleep state. In this paper, an algorithm has been given to determine the optimum input vector that(More)
  • 1