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Lattice Reduction (LR) is a promising technique to improve the performance of linear MIMO detectors. This paper proposes a Hybrid LR algorithm (HLR), which is a scalable LR algorithm. HLR is specifically designed and optimised to exploit ILP and DLP features offered by parallel programmable baseband architectures. Abundant vector-parallelism in HLR is(More)
Lattice Reduction aided soft output MIMO detectors (LR-SOMD) have been demonstrated to offer a promising gain. This work explores the potential of implementing a LR-SOMD on a parallel programmable baseband processor. In this paper, first a LR algorithm called the Data Regularized Parallel Lattice Reduction algorithm (DRP-LR) is proposed. Afterwards, a(More)
Lattice reduction is a promising technique to enhance the performance of sub-optimal MIMO detectors. This paper presents the Bounded Block Parallel Lattice Reduction (BBP-LR) algorithm, which is an implementation friendly low complexity algorithm specifically optimized for practical MIMO-OFDM systems. The optimisation of the BBP-LR algorithm is based on the(More)
We present the first implementation of a distributed beam-forming algorithm for interference mitigation on an SDR baseband processor. Co-channel interference (CCI) is becoming a major source of impairments in wireless communications and distributed beamforming is a promising technique to mitigate its negative impact. However, such schemes are challenging to(More)
Fixed-point arithmetic leads to efficient implementations. However, the optimization process required to size each of the implementation signals can be prohibitively complex. In this paper, we introduce a new divide-and-conquer method that is able to approach the quality of global methods in significantly less time. Firstly, our method sorts the signals in(More)
With the advent of heterogeneous MPSoC (Multi-Processors System-on-Chip) implementations of wireless applications, system partitioning and mapping has become a key challenge. To achieve efficient designs, system partitioning should simultaneously consider application characteristics, architecture constraints and physical design costs. It is also important(More)