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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TLDR
A 1.2 V 10-bit 100 MS/s Successive Approximation ADC achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Expand
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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
TLDR
An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. Expand
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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
TLDR
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. Expand
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A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation
TLDR
The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. Expand
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A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting
  • Y. Lu, Haojuan Dai, +4 authors R. Martins
  • Materials Science, Computer Science
  • IEEE Transactions on Circuits and Systems II…
  • 1 February 2017
TLDR
This brief presents a dual-path CMOS rectifier with adaptive control for ultrahigh-frequency (UHF) RF energy harvesters. Expand
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Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators
TLDR
An LCO reduction technique for the D-LDO is then proposed, by adding two unit power transistors in parallel with the main power MOS array as a feedforward path. Expand
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20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control
TLDR
This work presents an analog-assisted (AA) tri-loop control scheme for transient improvement, low power, and COUT reduction. Expand
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Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
  • Yan Zhu, C. Chan, +4 authors F. Maloberti
  • Computer Science, Mathematics
  • IEEE Transactions on Very Large Scale Integration…
  • 1 February 2014
TLDR
This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. Expand
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Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC
TLDR
This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. Expand
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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
TLDR
This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a high conversion rate and accuracy with good power efficiency. Expand
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