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An ATPG-based framework for verifying sequential equivalence
In this paper, we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removalExpand
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CMOS bridges and resistive transistor faults: IDDQ versus delay effects
Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailedExpand
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Logic optimization by an improved sequential redundancy addition and removal techniques
Logic optimization methods using automatic test pattern generation (ATPG) techniques such as redundancy addition and removal have recently been proposed. We generalize this approach for synchronousExpand
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Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects
Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation fromExpand
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Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation
Bridge-type defects play a dominant role in state-of-the-art CMOS technologies. This paper describes a combined functional and overcurrent-based test generation approach for CMOS circuits, which isExpand
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Improving topological ATPG with symbolic techniques
This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often failExpand
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MILEF: an efficient approach to mixed level automatic test pattern generation
Automatic test pattern generation in CMOS circuits from gate-level net lists is efficient, but has shortcomings with respect to fault coverage in complex and irregular CMOS gates and networks. AnExpand
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Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm
Automatic test pattern generation (ATPG) yielding high fault coverage for CMOS circuits has received a wide attention in industry and academia for a long time. Mixed level test pattern generationExpand
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SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information
Combining different techniques for sequential automated test pattern generation (ATPG) can help overcome their respective limits and exploit their advantages. In this paper, a hybrid techniqueExpand
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Gate delay fault test generation for non-scan circuits
This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on theExpand
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