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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
TLDR
A 1.2 V 10-bit 100 MS/s Successive Approximation ADC achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Expand
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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
TLDR
An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. Expand
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Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
  • Yan Zhu, C. Chan, +4 authors F. Maloberti
  • Computer Science, Mathematics
  • IEEE Transactions on Very Large Scale Integration…
  • 1 February 2014
TLDR
This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. Expand
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Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC
TLDR
This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. Expand
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A power effective 5-bit 600 MS/s binary-search ADC with simplified switching
TLDR
This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. Expand
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A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer
TLDR
This paper proposes a 40-nm CMOS output buffer with dynamic leakage and SR variation compensation and dynamic leakage reduction during signal transitions. Expand
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A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
TLDR
This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). Expand
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A C-less ASK demodulator for implantable neural interfacing chips
TLDR
We propose a C-less (no capacitor) area-saving ASK demodulator and a complete power regulator supplying a stable 3.3V VDD. Expand
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A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS
TLDR
This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Expand
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A multiparameter implantable microstimulator SOC
  • C. Wang, T. Lee, +4 authors Y. Hsueh
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration…
  • 1 December 2005
TLDR
We propose a C-less (no capacitor) area-saving ASK demodulator in this work to get rid of those large discrete capacitors required for low-frequency ASKE demodulation. Expand
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