U. Chio

Publications
Influence

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Yan Zhu, C. Chan, +4 authors F. Maloberti
Physics, Computer Science
IEEE Journal of Solid-State Circuits
7 June 2010

A 1.2 V 10-bit 100 MS/s Successive Approximation ADC achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Expand

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

H. Wei, C. Chan, +4 authors F. Maloberti
Physics, Computer Science
IEEE Journal of Solid-State Circuits
24 September 2012

An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. Expand

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

Yan Zhu, C. Chan, +4 authors F. Maloberti
Computer Science, Mathematics
IEEE Transactions on Very Large Scale Integration…
1 February 2014

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. Expand

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

U. Chio, H. Wei, +4 authors F. Maloberti
Computer Science
IEEE Transactions on Circuits and Systems II…
1 August 2010

This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. Expand

A power effective 5-bit 600 MS/s binary-search ADC with simplified switching

S. Wong, U. Chio, +4 authors R. Martins
Engineering
53rd IEEE International Midwest Symposium on…
16 August 2010

This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. Expand

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer

T. Lee, Tsung-Yi Tsai, W. Lin, U. Chio, C. Wang
Materials Science, Computer Science
IEEE Transactions on Very Large Scale Integration…
18 August 2017

This paper proposes a 40-nm CMOS output buffer with dynamic leakage and SR variation compensation and dynamic leakage reduction during signal transitions. Expand

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

C. Chan, Yan Zhu, U. Chio, Sai-Weng Sin, U. Seng-Pan, R. Martins
Computer Science, Engineering
IEEE Asian Solid-State Circuits Conference
1 November 2011

This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). Expand

A C-less ASK demodulator for implantable neural interfacing chips

C. Wang, Y. Hsueh, U. Chio, Yu-Tzu Hsiao
Engineering, Computer Science
IEEE International Symposium on Circuits and…
23 May 2004

We propose a C-less (no capacitor) area-saving ASK demodulator and a complete power regulator supplying a stable 3.3V VDD. Expand

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

H. Wei, C. Chan, +4 authors F. Maloberti
Engineering, Computer Science
IEEE International Solid-State Circuits…
7 April 2011

This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Expand

A multiparameter implantable microstimulator SOC

C. Wang, T. Lee, +4 authors Y. Hsueh
Engineering, Computer Science
IEEE Transactions on Very Large Scale Integration…
1 December 2005

We propose a C-less (no capacitor) area-saving ASK demodulator in this work to get rid of those large discrete capacitors required for low-frequency ASKE demodulation. Expand

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