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From opencl to high-performance hardware on FPGAS
TLDR
It is shown that the OpenCL computing paradigm is a viable design entry method for high-performance computing applications on FPGAs and that it can achieve a clock frequency in excess of 160MHz on benchmarks.
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An OpenCL(TM) Deep Learning Accelerator on Arria 10
TLDR
This work shows a novel architecture written in OpenCL(TM), which is referred to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth, and shows how the Winograd transform can be used to significantly boost the performance of the FPGA.
An OpenCL™ Deep Learning Accelerator on Arria 10
TLDR
This work shows a novel architecture written in OpenCL(TM), which is referred to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth, and shows how the Winograd transform can be used to significantly boost the performance of the FPGA.
View on ACM
Serializability of Transactions in Software Transactional Memory
TLDR
An obstruction-free STM system that uses CS with multi-versioning is implemented and evaluation shows that the use of CS significantly reduces abort rates in programs with high abort rates, resulting in up to 2.5 times improvement in throughput.
Hardware Support for Relaxed Concurrency Control in Transactional Memory
TLDR
This paper uses a technique which approximates conflict-serializability and implements it in hardware on top a base hardware transactional memory system that provides support for isolation and conflict detection and shows that it captures the benefits of conflict- serializability.
View on ACM
OpenCL for FPGAs: Prototyping a Compiler
TLDR
This paper presents a framework to support OpenCL compilation to FPGAs, and presents the compilation flow and the results on a set of benchmarks that show the effectiveness of the automated compiler.
Relaxed Concurrency Control in Software Transactional Memory
TLDR
This work proposes the use of a more relaxed concurrency control algorithm to provide better concurrency, based on the conflict-serializability (CS) model, which improves the performance of applications with long transactions and high abort rates.
View on IEEE
St Journal of Research -volume 1 -number 2 -processor Architecture and Compilation for Embedded Systems 4 Copyright © Ieee, 2004 -reprinted, with Permission, from a Multi-level Compauting…
4 COPYRIGHT © IEEE, 2004 REPRINTED, WITH PERMISSION, FROM A MULTI-LEVEL COMPAUTING ARCHITECTURE FOR EMBEDDED MULTIMEDIA APPLICATIONS, BY FARAYDON KARIM, ALAIN MELLAN, ANH NGUYEN (STMICROELECTRONICS),…
A multilevel computing architecture for embedded multimedia applications
TLDR
A new architecture that simplifies integration of heterogeneous IP for multimedia and streaming applications and supports a natural programming model that relieves programmers from explicitly synchronizing tasks and communicating data.
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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC
TLDR
This work proposes TensorTile ASICs for Stratix10 FPGAs to provide ASIC-level tensor performance, while relying on FPGA's flexibility for application-specific operations (e.g., Winograd).
View on ACM
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