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High complex control devices can be described by interactive FSMs (IFSMs) which can be derived from representations based on hardware description languages (VHDL or Verilog) [3]. The description of each FSM can be modified by adding the characteristic to be, in test mode, transparent to data flow. The complete testability of the IFSM is thus achieved by(More)
Control-dominated architectures are usually described in a hardware description language (HDL) by means of interacting FSMs. A VHDL or Verilog specification can be translated into an interacting FSM (IFSM) representation as described here. The IFSM model allows us to approach the testable synthesis problem at the level of each FSM. The functionality is(More)
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