Tzu-Jin Yeh

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In this paper, a novel circuit topology of CMOS divide-by-three injection-locked frequency divider is demonstrated. By using a differential direct injection pair with a LC-tank oscillator, the proposed circuit can perform the division ratio of three while the wide locking range is obtained. Based on the presented circuit architecture, a V-band frequency(More)
This paper presents two 60-GHz low-noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode-based and LC-based configurations. By codesigning ESD network and input matching, both LNAs are optimized for minimum noise figure (NF) while maintaining a similar gain. Compared with the conventional double-diode approach,(More)
Copper interconnects with and without the grounded shielding on the silicon substrate are modeled from 1 to 110GHz. The fully-analytical model is composed of the cascaded lumped resistor–inductor–conductor–capacitor (RLGC) circuit elements with 20 sections, and featured physical-based, scalable, and frequency-dependent characteristics. An excellent(More)
This paper presents a V-band low-noise amplifier with high RF performance and ESD robustness. An inductortriggered silicon-controlled rectifier (SCR) assisted with both a PMOS and an inductor is proposed to enhance the ESD robustness and minimize the impact of the ESD protection block on the millimeter-wave LNA. The initial-on PMOS improves the turn-on(More)
This paper studies the trade-off between different cell-based layout styles and V<sub>t</sub> options using a set of 5-GHz differential cascode LNAs. The test chip is fabricated in 65-nm CMOS process. The impact of merged diffusion area at the cascode node, the effect of gate contact style as well as the usage of normal V<sub>t</sub> versus low(More)
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