Tung-Hua Yeh

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A high-level test synthesis (HLTS) method targeted for delay-fault testability is presented in this paper. The proposed method, when combined with hierarchical test-pattern generation for embedded modules, guarantees a 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low(More)
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software development such as performance evaluation, speedup and bottleneck analysis, and system verification by taking the advantages of exploring many-core platforms in(More)
System-level interconnect structures become much more complicated and dominate overall performance in multi-core systems. In order to facilitate interconnect test in board-level and system-on-chip (SoC) designs, IEEE standards 1149.1 and 1500 are developed. Dedicated design-for-testability (DFT) architectures for interconnect consisting of through-silicon(More)
An effective clock-skew scheduling scheme in the high-level synthesis process targeted for power and speed optimization is presented. The proposed scheme has the following distinctive features: 1) a clock-skew management algorithm that selects a minimum set of clock phases to achieve the optimization goals is developed; 2) the effect of module binding in(More)
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embedded modules, guarantees 100% delay test coverage for detectable faults in modules. A study on the delay testability problem in behavior level shows that low delay fault coverage is(More)
In this paper, we proposed a test data compression scheme targeted for minimizing the amount of test data. The proposed scheme can reduce the test application time and minimize the amount of compressed test data, which reduces the size of data memory in ATE and the time needed to transfer test data. A decoder design is also presented. Experimental results(More)
High temperature in test process may invalidate a test due to extra delay, or even damage the circuit under test. Therefore, a thermal-safe test can avoid undesirable yield loss due to the extra delay induced by high temperature. Traditional high level test synthesis approaches just improve hierarchical testability of circuits and minimize test application(More)
High-level decisions have the most impact on power consumption, but the effect of those decisions cannot be known until the hardware is implemented. This paper walks the reader through an industrial high-level low-power design methodology that enables the designer to consider and quantitatively evaluate a broad range of hardware implementations to find the(More)
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