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—H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential,(More)
—Intra prediction with rate-distortion constrained mode decision is the most important technology in H.264/AVC intra frame coder, which is competitive with the latest image coding standard JPEG2000, in terms of both coding performance and computational complexity. The predictor generation engine for intra prediction and the transform engine for mode(More)
—Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore , we propose two hardware architectures(More)
In this paper, we contributed a new VLSI architecture for fractional motion estimation of H.264/AVC. Seven interrelated loops extracted from complex procedure are analyzed and two decomposing techniques are proposed to parallelize the algorithm for hardware with regular schedule and full utilization. The proposed architecture, also characterized by reusable(More)
—In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR).(More)
Direct VLSI implementation of context-based adaptive variable length coding (CAVLC) for residues, as a modification from conventional run-length coding, will lead to low lhroughgut and utilization. In this paper, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4x4-blocks. When(More)
An H.264/AVC encoder [1] saves 25% to 45% and 50% to 70% of bit rates when compared with MPEG4 and MPEG2, respectively. New features include 1 /4-pixel motion estimation (ME) with multiple reference frames (MRF) and variable block sizes (VBS), intra prediction, context-based adaptive variable length coding, deblocking, rate-distortion optimized mode(More)