Learn More
—H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for real-time applications. In addition, due to the complex, sequential,(More)
—Intra prediction with rate-distortion constrained mode decision is the most important technology in H.264/AVC intra frame coder, which is competitive with the latest image coding standard JPEG2000, in terms of both coding performance and computational complexity. The predictor generation engine for intra prediction and the transform engine for mode(More)
Variable block size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures,(More)
We contributed a new VLSI architecture for fractional motion estimation of the H.264/AVC video compression standard. Seven inter-related loops extracted from the complex procedure are analyzed and two decomposing techniques are proposed to parallelize the algorithm for hardware with a regular schedule and full utilization. The proposed architecture, also(More)
Epilepsy is one of the most common brain disorders in the world. The spontaneous seizure onset influences the daily life of epilepsy patients. The studies on feature extraction and feature classification from Electroencephalography(EEG) signal in seizure prediction methods have shown great improvement these years. However, the variation issue of EEG signal(More)
An H.264/AVC encoder [1] saves 25% to 45% and 50% to 70% of bit rates when compared with MPEG4 and MPEG2, respectively. New features include 1 /4-pixel motion estimation (ME) with multiple reference frames (MRF) and variable block sizes (VBS), intra prediction, context-based adaptive variable length coding, deblocking, rate-distortion optimized mode(More)
In motion estimation, fast algorithms usually lead to an irregular searching flow, and the power reduction on architecture level is constrained for poor data reuse (DR). In this paper, a parallel IME hardware for H.264/AVC is proposed to well combine the techniques on algorithm and architecture levels. The "2-D SAD Tree" is adopted to support intra- and(More)
Direct VLSI implementation of context-based adaptive variable length coding (CAVLC) for residues, as a modification from conventional run-length coding, will lead to low throughput and utilization. In this paper, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4/spl(More)