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Introduction Parallel Genetic Algorithms (PGAs) have frequently been cited as an important area of research as they provide a means of rapidly developing a solution to a wide range of problems. Real-time image analysis is one of the areas of research which would particularly benefit from PGAs, however such algorithms are generally simulated on conventional(More)
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique based on branch metric normalization is introduced to improve the speed performance of the decoder. The turbo decoder with the proposed technique has been synthesized to evaluate(More)
A technique for the structural synthesis of VLSI circuits is presented. The technique uses a Genetic Algorithm which utilises a library of devices for the synthesis procedure which proved successful in searching a highly complex space of structures by producing designs which satisfy a multiple output circuit criteria which, in addition to satisfying the(More)
— This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16×16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we(More)
The authors present a reconfigurable soft-input soft-output (SISO) turbo decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with a sliding window (SW) method. The turbo decoder is designed to support constraint lengths from 3 to 5 and synthesized to a 0.18um standard CMOS cell library. Power and area overheads for the(More)
—This paper proposes a low power commutator architecture for the implementation of radix-4 based pipelined Fast Fourier Transform processor. The architecture is based on dual port RAM blocks and exploits the interconnection topology among these blocks for low power implementation. The paper presents the commutator architecture, describes the design(More)
Advanced microcontroller bus architecture (AMBA) is rapidly becoming the de facto standard for new system-on-chip (SoC) designs. The bus protocol is complex, making any peripherals that can interface to it valuable intellectual property (IP). This paper presents a low-power bus encoding architecture which is able to deal with the complex advanced(More)
The foundations for building the first Reliable Reconfigurable Real-Time Operating System (R3TOS) are presented. The main objective of R3TOS is to create an infrastructure for coordinately executing specialized hardware tasks upon a reconfigurable FPGA device, achieving the necessary flexibility for both gaining system performance (true hardware(More)