Tsz-leung Cheung

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  • App, A W Appel, +16 authors K Wong
  • 1998
[Ayc00] P. Aycinena, " IP reuse called essential to advanced chip designs " , [Cad99] Cadence Design System, Cadence delivers industry's first tool integrating synthesis and place-and-route technologies, Timing optimazation on routed designs with incremental placement and routing characterization, " IEEE Trans.
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