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The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The(More)
A 4-phase cross-coupled charge pump with charge sharing clock scheme is proposed in this paper. Four phase clock is utilized to prevent the reverse leakage current. A charge sharing clock control circuit is constructed, and the consumption in charging or discharging the bottom plate parasitic capacitance of the boost capacitors is reduced by half. The(More)
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also(More)