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A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm<sup>2</sup>. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels… (More)
This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm<sup>2</sup> tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
individually and shorten the verification time during SoC integration. In this paper, we will introduce the implemented environment of 3DG SoC and elucidate significance and necessary of proposed method. For the convenience of verification, the analyzing tool that we have developed contains the functions of displaying frame results, comparing different… (More)
This paper presents an embedded debugging/performance monitoring engine (EDPME), which is capable of collect run time characteristics, detect AHB on-chip bus protocol error/inefficiency, and capture on-chip AHB bus traces at various abstraction levels with compression ratio up to 98% for a low cost tile-based 3D graphics SoC development.
Dependency structure matrix genetic algorithm (DSMGA), one of estimation of distribution algorithms (EDAs), adopts model-building mechanisms via dependency structure matrix clustering techniques. Previous researches have shown that DSMGA can effectively solve nearly decomposable problems. DSMGA utilizes an entropy-based metric to detect the interactions… (More)
The problem addressed in this paper-the linehaul-feeder vehicle routing problem with virtual depots (LFVRP-VD)-can be regarded as an extension of the vehicle routing problem. During delivery operation, one large vehicle departs from the physical depot (PD) and services all virtual depots (VDs). A set of small vehicles delivers to customers and, if… (More)
In designing the portable embedded system, power consumption would be an important issue. Numerous prior issues of power dissipation have been discussed, and there are fewer functions (such as power measurement, power analysis, and power management) supporting for a SoC embedded system development learning board. In order to help designer to get power… (More)
This work proposes a test function to study overlapping. The test function provides full controllability over overlapping. To achieve full controllability, the building block assigning problem is reduced to a bipartite matching problem which allow us to directly assign extent of overlapping to each gene. At the end, an experiment on overlapping shows that… (More)
This work proposes a linkage-learning niching method that improves the capability of estimation of distribution algorithms (EDAs) on reducing spurious linkages which increase problems difficulty. Concatenated parity function (CPF), a class of allelic pairwise independent problems, causes exponential scalability for hierarchical Bayesian optimization… (More)
In order to solve the system performance bottleneck of a 3D graphics acceleration SoC, we exploit design space exploration on performance evaluation and benchmark characteristics using SystemC. We find out the bottleneck according to the simulation results of 9 hardware/software configurations and find out the tradeoffs between different configurations. The… (More)