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The problem addressed in this paper-the linehaul-feeder vehicle routing problem with virtual depots (LFVRP-VD)-can be regarded as an extension of the vehicle routing problem. During delivery operation, one large vehicle departs from the physical depot (PD) and services all virtual depots (VDs). A set of small vehicles delivers to customers and, if(More)
A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm<sup>2</sup>. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels(More)
This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm<sup>2</sup> tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
This paper proposes an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification methodology,(More)
This work proposes a test function to study overlapping. The test function provides full controllability over overlapping. To achieve full controllability, the building block assigning problem is reduced to a bipartite matching problem which allow us to directly assign extent of overlapping to each gene. At the end, an experiment on overlapping shows that(More)
Dependency structure matrix genetic algorithm (DSMGA), one of estimation of distribution algorithms (EDAs), adopts model-building mechanisms via dependency structure matrix clustering techniques. Previous researches have shown that DSMGA can effectively solve nearly decomposable problems. DSMGA utilizes an entropy-based metric to detect the interactions(More)
This paper presents an embedded debugging/performance monitoring engine (EDPME), which is capable of collect run time characteristics, detect AHB on-chip bus protocol error/inefficiency, and capture on-chip AHB bus traces at various abstraction levels with compression ratio up to 98% for a low cost tile-based 3D graphics SoC development.
This paper investigates the difficulty for linkage learning with restricted tournament replacement (RTR), which is the well-known niching on the success of solving difficult problems, such as hierarchical trap problems. It is mysterious that RTR has difficulty dealing with concatenated parity function (CPF) problem that is easy for simple GA casually. The(More)
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