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(a) (b) (c) (d) Figure 1: An overview of image-based BRDF acquisition. (a) An object of arbitrary shape that we will capture the BRDF from. (b) A real photograph of cloth. (c) A synthetic image of the same cloth, but applied with the BRDF captured from (a). (d) A synthetic image under another lighting condition. Abstract In order to create photorealistic(More)
—In recent years, the chip leakage power may be larger than the chip dynamic power because the semiconductor process technology progresses quickly. Therefore, leakage power reduction becomes an important issue for low power circuit designers. In this paper, we propose a heuristic cell replacement algorithm to reduce the leakage power of a logic design. The(More)
Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and(More)
—Data hazards cause severe pipeline performance degradation for data-intensive computing processes. To improve the performance under a pessimistic assumption on the pipeline efficiency, a high-speed and energy-efficient VLSBM is proposed that successively performs a speculating and correcting phase. To reduce the critical path, the VLSBM partial products(More)
In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising(More)