Tsung-Han Tsai

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Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing(More)
Optical higher harmonic generation, including second harmonic generation and third harmonic generation, leaves no energy deposition to its interacted matters due to an energy-conservation characteristic, providing the "noninvasiveness" nature desirable for biological studies. Combined with its nonlinearity, higher harmonic generation microscopy provides(More)
Optical second- and third-harmonic generations have attracted a lot of attention in the biomedical imaging research field recently due to their intrinsic sectioning ability and noninvasiveness. Combined with near-infrared excitation sources, their deep-penetration ability makes these imaging modalities suitable for tissue characterization. In this article,(More)
We study the problem of optimally adapting ongoing cloud gaming sessions to maximize the gamer experience in dynamic environments. The considered problem is quite challenging because: (i) gamer experience is subjective and hard to quantify, (ii) the existing open-source cloud gaming platform does not support dynamic reconfigurations of video codecs, and(More)
The parallel connected component labeling used in binary image analysis is reconsidered in this paper for the high throughput and intermediate memory requirements problem on high dimensional image sequence. It is based on a proposed dual-parallel connected component labeling method. The main idea is to break the sequentiality of the labeling procedure by(More)
In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The(More)