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On-chip interconnect exhibits clear frequency-dependence in both resistance and inductance. A compact ladder circuit model is developed to capture this behavior , and we examine its impact on digital and RF circuit design. It is demonstrated that the use of DC values for R and L is sufficient for delay analysis, but RL frequency dependence is critical for(More)
Deep-sub-tenth micron MOSFETS with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel " Folded Channel Transistor " structure is proposed. The quasi-planar nature of this n~ew variant of the vertical double-gate SOI MOSFETS [1],[2] simplified the fabrication process. The special features of the structure (Fig. 1)(More)
—Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM(More)
Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise(More)
Semiconductor flash memory is an indispensable component of modern electronic systems. The minimum feature size of an individual CMOSFET has shrunk to 15nm with an equivalent gate oxide thickness (EOT) of 0.8nm in 2001. However, semiconductor flash memory scaling is far behind CMOS logic device scaling. For example, the EOT of the gate stack in(More)
1. Introduction Power has become a primary design constraint in digital integrated circuits. Most designs in sub-100nm technologies will either maximize the performance under power constraints or minimize the energy for required amount of computation. To achieve the optimality in power-performance space, integrated circuits have to be optimized at all(More)
Metal gate materials will be necessary to eliminate the gate depletion effect [l] and to control threshold voltage for high-performance thin-body transistors [2] in future CMOS technologies. Metals with tunable work-function such as molybdenum (MO) [3] and tantaldruthenium alloys [4] are of particular interest, because they can potentially simplify(More)
Polycrystalline silicon (poly-Si) has been used as the gate material for MOSFETs for several decades. This is because it is highly compatible with CMOS processing, and its work function can be selectively modified by ion implantation of the appropriate dopants. The gate-depletion effect, which increases the equivalent SiO 2 thickness (EOT) of the gate(More)