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—MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si 0 4 Ge 0 6 as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate(More)
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an I dsat of 410 2A/2m (or 820 2A/2m depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The(More)
Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45nm CMOS technologies. Nonclassical transistor structures such as the FinFET are likely necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it(More)
Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise(More)
In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling between(More)
—Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM(More)
On-chip interconnect exhibits clear frequency-dependence in both resistance and inductance. A compact ladder circuit model is developed to capture this behavior , and we examine its impact on digital and RF circuit design. It is demonstrated that the use of DC values for R and L is sufficient for delay analysis, but RL frequency dependence is critical for(More)
Figure 1: The thin-body silicide source/drain MOSFET in cross section. Source/drains are made in 100Å Si: NMOS uses ErSi1.7 (Φb0n=0.28V), PMOS uses PtSi (Φb0p=0.24V). Spacer thickness is limited to 100Å, in order to guarantee that the metal diffuses underneath the gate. Abstract Thin-body transistors with silicide source/drains were fabricated with(More)
Continued scaling of CMOS technology beyond the 100 nm technology node will rely on fundamental changes in transistor gate stack materials [1]. Refractory metals and their metallic derivatives are among the only candidates suitable for use as transistor gate electrodes. In earlier publications, Mo has been proposed as a potential candidate for use as a(More)
In this work, MOSFETs with gate oxides between 9 to 13 A have been fabricated and its behavior analyzed. An improved methodology of extracting gate oxide thickness from the MOSFET gate currents in the accumulation regime is proposed. Experimental evidence for mobility reduction mechanism, namely Remote Charge Scattering has been presented. The mobility was(More)