Tsu-Jae King

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MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si0 4Ge0 6 as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs(More)
High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. 45 nm gate-length PMOS FinFET has an Idsat of 410 PA/Pm (or 820 PA/Pm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The(More)
Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise(More)
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM(More)
Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15nm. Complementary low-barrier silicides were used to reduce contact and series resistance. Minimum gate-length transistors with Tox=40Å show PMOS |Idsat|=270μA/μm and NMOS |Idsat|=190μA/μm with Vds=1.5V, |Vg-Vt|=1.2V and, Ion/Ioff>10 . A simple transmission model,(More)
Abstract In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the ability to control off-state leakage current due to quantum tunneling and thermionic emission between the source and drain as well as band-to-band tunneling(More)
On-chip interconnect exhibits clear frequencydependence in both resistance and inductance. A compact ladder circuit model is developed to capture this behavior, and we examine its impact on digital and RF circuit design. It is demonstrated that the use of DC values for R and L is sufficient for delay analysis, but RL frequency dependence is critical for the(More)
Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45nm CMOS technologies. Nonclassical transistor structures such as the FinFET are likely necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it(More)
The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor ~MOS! gate stacks was explored. Metal work functions on high-k dielectrics are observed to differ appreciably from their values on SiO2 or in vacuum. We applied the interface dipole theory to the interface between the gate and the gate(More)
In this work, MOSFETs with gate oxides between 9 to 13 A have been fabricated and its behavior analyzed. An improved methodology of extracting gate oxide thickness from the MOSFET gate currents in the accumulation regime is proposed. Experimental evidence for mobility reduction mechanism, namely Remote Charge Scattering has been presented. The mobility was(More)