Trung N. Nguyen

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We present several new compiler techniques employed by our interprocedural parallelizing research compiler, Panorama, to improve loop parallelization and the eeciency of memory references. We rst present an overview of the compiler and its associated memory architecture simulation environments. We then present an interprocedural array dataaow analysis,(More)
In order to reduce remote memory accesses on CC-NUMA multiproces-sors, we present an interprocedural analysis to support static loop scheduling and data allocation. Given a parallelized program, the compiler constructs graphs which represent globally and interprocedurally the remote reference penalties associated with diierent choices for loop scheduling(More)
{ In the decision regarding static scheduling vs. dynamic scheduling, the only argument against the former is the potential imbalance of the workload. However, it has never been clear how the workload distributes in the iterations of Fortran parallel loops. This work examines a set of Perfect benchmarking programs 2] and report two striking results. First,(More)
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