Trong-Yen Lee

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In this paper, we propose an enhancement partition method that incorporates formal partition, fitting system constraints and hardware orient partition algorithm to solve partitioning issue for embedded multiprocessor FPGA systems. With formal partition, we can rapidly obtain a set of partitioning results that satisfy the system constraints on the number of(More)
The design of multiprocessor architectures differs from uniprocessor systems in that the number of processors and their interconnection must be considered. This leads to an enormous increase in the design-space exploration time, which is exponential in the total number of system components. The methodology proposed here, called <italic>Intelligent(More)
The growing complexity of embedded real-time software requirements calls for the design of reusable software components, the synthesis and generation of software code, and the automatic guarantee of nonfunctional properties such as performance, time constraints, reliability, and security. Available application frameworks targeted at the automatic design of(More)
Most of current codesign tools or methodologies only support validation in the form of cosimulation and testing of design alternatives. The results of hardware-software codesign of a distributed system are often not verified, because they are not easily verifiable. In this paper, we propose a new formal coverification approach based on linear hybrid(More)
Embedded real-time applications are often built from scratch on a trial-and-error basis, which leads to sub-optimal designs with latent errors that are not detectable in early stages of use or deployment and often incurs prolonged time-to-market. A new application framework called Verifiable Embedded Real-Time Application Framework (VERTAF) is proposed for(More)
This work proposes a hardware-software partitioning approach named GHO to solve the partitioning issue for embedded multiprocessor FPGA systems. GHO adopts genetic algorithm and hardware-oriented partition to improve the partitioning result with faster execution time, smaller memory size and higher slice usage under satisfied system constraints. Two(More)
Nowadays, the hardware of field programmable gate arrays (FPGAs) can be reconfigured both dynamically and partially. A dynamically and partially reconfigurable system can share hardware contexts among various hardware tasks. However, such FPGA systems require much memory to save the hardware context. To solve this problem, this work proposes a methodology(More)
An embedded multiprocessor FPGA system can provide powerful and more functionalities than single processor system. However, the hardware-software partitioning problem is more complex in system design because the system components become escalation. In this paper, we propose a sophisticated computation method (SCM) to solve hardware-software partitioning(More)
In recent years, task placement technology for reconfigurable FPGA has been developed into 2-D arrays. In this paper, we propose a methodology to pre-place hardware resource into multi-area to achieve the high utilization of hardware resource and reduce used area. The method solves the task type placement problems on the partial dynamic reconfigurable(More)