Trevor J. Thornton

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The study of the behavior of ion-channels can provide significant information to detect metal ions and small organic molecules in solution. Discrimination of different analytes can be performed by extracting appropriate features from the ion-channel signals and using them for classification. In this paper, we consider features extracted from the Fourier,(More)
We demonstrate the microfabrication of a low-noise silicon based device with integrated silver/silver chloride electrodes used for the measurement of single ion channel proteins. An aperture of 150 microm diameter was etched in a silicon substrate using a deep silicon reactive ion etcher and passivated with 30 nm of polytetrafluoroethylene via chemical(More)
Enhanced voltage silicon metal-semiconductor-field-effect-transistors (MESFETs) have been fabricated on a 45 nm SOI CMOS technology with no process changes. MESFETs scaled to L<sub>g</sub> = 184 nm were fabricated and show a peak f<sub>T</sub> of 35 GHz, current drive of 112 mA/mm and breakdown voltages exceeding 4.5 V whereas the nominal CMOS voltage was(More)
A CMOS low dropout linear regulator (LDO) with a MESFET based follower output stage was designed and fabricated on a commercial 45nm SOI CMOS technology. The proposed LDO demonstrates a dropout voltage of &lt;;170mV at 1A load current while occupying 0.245mm<sup>2</sup> of die area. The approach includes a novel depletion mode n-channel MESFET in a low(More)
A close-packed monolayer of zinc 5,10,15,20-tetrakis(3-carboxyphenyl)porphyrin has been prepared and deposited on the thin native oxide covering the surface of an SOI-MOSFET (silicon-on-insulator metal-oxide-semiconductor field effect transistor) using Langmuir-Blodgett techniques. When the device is exposed to amine vapors in a nitrogen atmosphere, the(More)
In this paper, a novel wireless sensor network discovery algorithm is presented which estimates the locations of a large number of low powered, randomly distributed sensor nodes. Initially, all nodes are at unknown locations except for a small number which are termed the &#x201C;anchor&#x201D; nodes. The remaining nodes are to be located as part of the(More)
CMOS compatible, high voltage SOI MESFETs have been fabricated using a standard 3.3V CMOS process without any changes to the process flow. A 0.6μm gate length device operates with a cut-off frequency of 7.3GHz and a maximum oscillation frequency of 21GHz. There is no degradation in device performance up to its breakdown voltage, which greatly exceeds that(More)
This article describes 40V N-channel MESFETs fabricated at a commercial 32nm SOI CMOS foundry without changing any of the process flow or including additional mask steps. The 32nm technology node is the most advanced technology node to date for MESFET fabrication and builds upon previous work completed at other process nodes. High voltage MESFETs were(More)
This work describes an improved Angelov/Chalmers MESFET model which includes substrate bias effects. The 4-terminal model employs a new and simplified gate current extraction method based on a forward and reverse diode equation which can be independently modified. The improved model is applied to a silicon metal-semiconductor-field-effect-transistor(More)