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abstract Two approaches have been used to balance the cost of generating eeective tests for ICs and the need to increase the ICs' quality level. The rst approach favors using high-level fault models to reduce test generation costs at the expense of test quality, and the second approach favors the use of low-level, technology-speciic fault models to increase(More)
The advantage to " one test at a time " fault diagnosis is its ability to implicate the components of complicated defect behaviors. The disadvantage is the large size and opacity of the diagnostic answer. In this paper, we address the problems of pertest fault diagnosis by improving the candidate matching, introducing scoring and ranking techniques, and by(More)
Robust path-delay test generator for standard scan designs. A new approach to derive robust tests for stuck-open faults in CMOS combinational logic circuits. We presented a new fault simulation algorithm for realistic CMOS network breaks. We showed that Miller feedback and feedthrough eeects can invalidate a test for a network break just as charge sharing(More)
Abstract: Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnosing bridging faults using single stuck-at dictionaries was applied only to small circuits, produced large and imprecise diagnoses, and did not take into account the Byzantine Generals Problem for bridging faults. We analyze the original technique(More)