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This article describes the Boolean satissability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diierence between the unfaulted and faulted circuits. Second, it applies a Boolean satissability algorithm to(More)
abstract Two approaches have been used to balance the cost of generating eeective tests for ICs and the need to increase the ICs' quality level. The rst approach favors using high-level fault models to reduce test generation costs at the expense of test quality, and the second approach favors the use of low-level, technology-speciic fault models to increase(More)
The advantage to " one test at a time " fault diagnosis is its ability to implicate the components of complicated defect behaviors. The disadvantage is the large size and opacity of the diagnostic answer. In this paper, we address the problems of pertest fault diagnosis by improving the candidate matching, introducing scoring and ranking techniques, and by(More)
Robust path-delay test generator for standard scan designs. A new approach to derive robust tests for stuck-open faults in CMOS combinational logic circuits. We presented a new fault simulation algorithm for realistic CMOS network breaks. We showed that Miller feedback and feedthrough eeects can invalidate a test for a network break just as charge sharing(More)
Diagnostic fault simulation can generate enormous amounts of data. The techniques used to manage this data can have signiicant eeect on the outcome of the fault diagnosis procedure. We rst demonstrate that if information is removed from a fault dictionary, its ability to diagnose unmodeled faults may be severely curtailed even if dictionary quality metrics(More)