Toshiyuki Sakamoto

Learn More
We present a tool that automatically generates a run-time scheduler for a target architecture from a heterogeneous system-level speciication in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented in software(More)
We present a hardware synthesis system that accepts system-level specications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input specications is to support hardware/software c o-design by allowing the migration to hardware of system modules(More)
We present a tool that automatically generates a run-time scheduler for a target architecture from a heterogeneous system-level specification in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented in(More)
  • 1