Toshiyuki Sakamoto

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We present a tool that automatically generates a run-time scheduler for a target architecture from a heterogeneous system-level speciication in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented in software(More)
An experiment was conducted to investigate the performance of an electrocardiogram (ECG) telemonitor using mobile Internet connections for telemedicine. The RTP/UDP protocol was used for data transmission. Packet loss was observed and an algorithm for error correction was introduced. The experiment showed that the data loss was relative to the packet size.(More)
We present a hardware synthesis system that accepts system-level specications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input specications is to support hardware/software c o-design by allowing the migration to hardware of system modules(More)
A secure and efficient scheme to rekey group keys is investigated. A group key is secret information which is owned by all users in a certain group. When a user newly joins the group, and when a user leaves the group, the group key must be updated, or rekeyed, to conform the security. Widely known LKH scheme works efficiently if its internal key-tree is(More)
An electrocardiogram telemonitor using 3G cellular phone was developed. The cellular phone works completely in wireless environments through using Bluetooth device. Communication performance of the cellular phone is investigated. Experiments of the investigation are conducted in five different places with different populations or in the moving status to(More)
We present a tool that automatically generates a run-time scheduler for a target architecture from a heterogeneous system-level specification in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented in(More)
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