Toshiro Akino

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Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed image sensor capable of on-chip signal accumulation. The very high frame rate is enabled by employing an image(More)
Our experience in the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate is the signal electron transit time from the generation layer at the back side of(More)
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the gated lateral npn or pnp BJT inherent of nor p-channel MOSFETs. Forward current is applied to the base terminal of the channel MOSFETs, with a normal pull-up or pull-down MOSFET as(More)
A mask analysis program for MOS/LSI mask layout data has been developed. This program converts all the mask layout data in one chip LSI into the corresponding circuit schema. A partitioning method for the large random logic circuit divides it into small sub-circuits. It is shown that this method takes full advantage of the savings both in computer time and(More)
A new operation mode for a lateral unified-complementary BiCMOS (hereafter abbreviated as U-CBiCMOS) buffer driver based on a partially depleted CMOS/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a nor p-channel MOSFET. Forward current is applied to the base terminal of the channel MOSFET, with a normal pull-up or pull-down(More)
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