Toshinori Sato

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0272-1732/00/$10.00  2000 IEEE Processors designed for computer entertainment must perform 3D graphics calculations, especially geometry and perspective transformations. In the PlayStation2, we introduced the idea of synthesizing emotion called Emotion Synthesis and devised a new processor architecture to support its graphics demands. The architecture is(More)
Operand bypass logic is likely to be one of the critical structures for future microprocessors to achieve high clock speed. The logic delay causes the execution time budget to be reduced significantly, so that the execution stage is divided into several stages. The variable latency pipeline (VLP) structure has the advantages of pipelining and(More)
Global interconnect becomes the delay bottleneck in microprocessor designs, and latency for large on-chip caches will be intolerable in deep submicron technologies. The recently-proposed Non-Uniform Cache Architectures (NUCAs) exploit the variation in access time across subarrays to reduce typical latency. In the dynamic NUCA (D-NUCA) design, a(More)
Modern microprocessors schedule instructions dynamically in order to exploit instruction level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is di cult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant(More)
The deep sub micron semiconductor technologies increase parameter variations. The increase in parameter variations requires excessive design margin that has serious impact on performance and power consumption. In order to eliminate the excessive design margin, we are investigating canary Flip-Flop (FF). Canary FF requires additional circuits consisting of(More)