Toshinobu Matsuba

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A novel high-level synthesis (HLS) technique to improve the clock frequency is presented. Our technique aims at the reduction of the clock period by eliminating interconnections, specifically multiplexers (MUXs). MUXs are generally inserted before shared functional units and shared registers. However, MUXs are also inserted before a register even if the(More)
As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique for reducing MUXs, especially during the earlier design phase, has been demanded. This paper presents a(More)
For FPGA-based designs generated through high-level synthesis (HLS), effects of resource sharing/unsharing on clock frequency, execution time, and area are quantitatively evaluated for several practically large benchmarks on multiple FPGA devices. Through experiments, we observed five important findings about resource sharing/unsharing, which are contrary(More)
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