Toshikazu Sekine

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— This paper proposes a novel two-phase drive adi-abatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and resembles behavior of static CMOS. As a result, the delay time of the 2PADCL is shorter than that of the conventional ADCL circuit in the second and subsequent stages. The structure of(More)
—Numerous articles and patents on the masking of logic gates in CMOS logic styles have been reported, however, less information is available with regards to comparing the single-rail and dual-rail on masking input logic values. This paper investigates single-rail and dual-rail logic families that have been developed by the logic designers for secure logic(More)
—This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 —m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared.(More)
— This paper presents the simulation results of a 4ˆ4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 —m standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit(More)
This paper proposes a memristor SPICE model using the Tukey window (or tapered cosine window) function. Compared with the previously proposed models based on the boundary function, the proposed model is resistant to numerical errors. From the SPICE result of a relaxation oscillator, we observe that the proposed model can be effectively used to minimise the(More)