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- Hironori Banba, Hitoshi Shiga, +4 authors Koji Sakui
- 1999

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply. In the conventional BGR circuit, the output voltage Vref is the sum of the built-in voltage of the diode Vf and the thermal voltage VT of kT=q multiplied by a constant. Therefore, Vref is about 1.25 V, which limits a low supply-voltage operation… (More)

- Tomoharu Tanaka, Mark Helm, +58 authors Camila Jaramillo
- ISSCC
- 2016

- Toru Tanzawa, Hiroyuki Shibayama, +9 authors Fumitoshi Hatori
- Proceedings of the IEEE 2004 Custom Integrated…
- 2004

The frequency drift of an open-loop PLL is an issue for direct modulation applications such as Bluetooth transceivers. The drift mainly comes from the temperature variation of the VCO during the TX operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through full-chip thermal analysis. Moreover, a novel… (More)

Focusing on internal high-voltage ( ) switching and generation for low-voltage NAND flash memories, this paper describes a switch, row decoder, and charge-pump circuit. The proposed nMOS switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination… (More)

- Toru Tanzawa
- IEEE Trans. on Circuits and Systems
- 2010

This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the… (More)

- Raymond Zeng, Navneet Chalagalla, +31 authors Hiroyuki Yokoyama
- ISSCC
- 2009

- Toru Tanzawa
- ISCAS
- 2008

- Toru Tanzawa
- ISCAS
- 2009

Parasitic resistance in power and ground lines is considered for Dickson charge pump circuit designs, and its equivalent model is modified for low voltage IC designs. When the optimization is done for maximized output current or for minimized rise time, it is not necessary to increase the number of stages, but it is necessary to increase the pumping… (More)

- Toru Tanzawa
- ICECS
- 2014

- Toru Tanzawa
- IEEE Trans. on Circuits and Systems
- 2010