Tooraj Nikoubin

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Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New(More)
In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design(More)
Carry Select Adder (CSLA) is used for arithmetic operations for better speed at the expense of area and power. In this paper we present novel structure of Conditional Binary to Excess-1 adder based on carry select adder design on gate level. Regular CSLA is area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be(More)
This paper presents four novel circuits for 7-bit Binary to BCD conversion. The first and second designs are modification of 3-3-1[1] algorithm with novel building blocks, which makes it area and delay efficient in comparison with previous design. The third circuit is the novel implementation of the shift-add algorithm that makes this design area efficient(More)
This paper addresses an ab-initio field investigation around using low-cost portable radars to capture coherent Doppler signatures of wind turbines for structural health monitoring (SHM) applications. A handheld low-cost K-band radar sensor is employed to point at the blades of a turbine, and their Doppler signatures from different angles and distances are(More)
Transistor sizing is very important for determination of the circuit performance. As a result for providing fair evaluation, an optimal size of transistor is necessary. Genetic algorithm that is capable of reduction of search problem complexity uses the transistor sizing which is originally a kind of search problem in the large multidimensional search space(More)
Two new high-performance Full Adders, purely designed with 3-input Majority-not function, are proposed in this paper. The Majority-not function is implemented efficiently by using only capacitors and a static CMOS inverter. This kind of design improves the parameters of the Full Adder cell and leads to high performance, driving capability, a high degree of(More)