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Conventional error correction codes (ECCs), such as the commonly used BCH code, have become increasingly inadequate for solid state drives (SSDs) as the capacity of NAND flash memory continues to increase and its reliability continues to degrade. It is highly desirable to deploy a much more powerful ECC, such as low-density parity-check (LDPC) code, to(More)
BACKGROUND A clinical trial that compared erlotinib with a placebo for non-small-cell lung cancer demonstrated a survival benefit for erlotinib. We used tumor-biopsy samples from participants in this trial to investigate whether responsiveness to erlotinib and its impact on survival were associated with expression by the tumor of epidermal growth factor(More)
—As technology continues to scale down, NAND Flash memory has been increasingly relying on error-correction codes (ECCs) to ensure the overall data storage integrity. Although advanced ECCs such as low-density parity-check (LDPC) codes can provide significantly stronger error-correction capability over BCH codes being used in current practice, their(More)
PURPOSE To evaluate the effect of KRAS and epidermal growth factor receptor (EGFR) genotype on the response to erlotinib treatment in the BR.21, placebo-controlled trial. PATIENTS AND METHODS We analyzed 206 tumors for KRAS mutation, 204 tumors for EGFR mutation, and 159 tumors for EGFR gene copy by fluorescent in situ hybridization (FISH). We reanalyzed(More)
Recently a novel algorithm transformation was proposed to reduce the critical path of Berlekamp-Massey algorithm implementation for errors-alone Reed-Solomon decoding. In this paper, we apply the same methodology to transform the Berlekamp-Massey algorithm for errors-and-erasures RS decoding. We present a regular hardware architecture to implement the(More)
Handbook of Signal Processing Systems provides a standalone, complete reference to signal processing systems organized in four parts. The first part motivates representative applications that drive and apply state‐of‐ the art methods for design and implementation of signal processing systems; the second part discusses architectures for implementing these(More)
This paper advocates a device-aware design strategy to improve various NAND flash memory system performance metrics. It is well known that NAND flash memory program/erase (PE) cycling gradually degrades memory device raw storage reliability, and sufficiently strong error correction codes (ECC) must be used to ensure the PE cycling endurance. Hence, memory(More)
Due to its great scalability potential, phase change memory has become a topic of great current interest. However, high write energy consumption appears to be one of the biggest challenges to be tackled before phase change memory can be adopted as a mainstream memory technology. This paper presents architecture level technique to reduce phase change memory(More)
We proposed a novel self-reference sensing scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) to overcome the large bit-to-bit variation of Magnetic Tunneling Junction (MTJ) resistance. Different from all the existing schemes, our solution is nondestructive: The stored value in the STT-RAM cell does NOT need to be overwritten by a reference(More)