Tong-Chern Ong

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A 1Mb STT-MRAM implemented in 2-cell per bit architecture is demonstrated in 40nm technology. By using newly developed sense amplifier and word-line driver as well, 300MHz access speed can be acquired and, compared to one cell per bit using conventional sensing scheme, huge immunity to PVT variation can be achieved. This paper shows an effective(More)
The gate voltage-induced current crowding (GVICC) effect [1] had been found as the root cause of that high voltage tolerant I/O (HVT I/O) failed at low-voltage ESD event. Based on this finding, a new pre-driver design is proposed to pull down the voltages of top gate and bottom gate of the cascode NMOS to 0V during ESD zapping event for eliminating the(More)
In this paper, we present a new erase gate disturb mechanism during programming of selected cell for split-gate Flash memory. This type of disturb occurs on the programmed cell sharing the same erase gate as the selected cell. The disturb is due to electron-loss from floating gate to erase gate caused by low-field Fowler-Norheim (F-N) tunneling. We proposed(More)
In this paper, a new latch-up phenomenon, in which the positive trigger voltage V/sub trg+/ is smaller than the theoretical value, based on the two-step activation diode model, is found and analyzed by TCAD simulation. Based on the simulation result, an analytical model for the positive trigger point is developed and methodologies for evaluating the(More)
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