Tong-Chern Ong

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The gate voltage-induced current crowding (GVICC) effect [1] had been found as the root cause of that high voltage tolerant I/O (HVT I/O) failed at low-voltage ESD event. Based on this finding, a new pre-driver design is proposed to pull down the voltages of top gate and bottom gate of the cascode NMOS to 0V during ESD zapping event for eliminating the(More)
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