Tomoyoshi Kataoka

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through(More)
This paper reports, for the first time, a 43-Gbit/s OTN interface prototype that implements more system functions than optical sending/reception, such as framing, scrambling/de-scrambling, client mapping, and supervisory functions, all with high performance. 1. Introduction Spectral efficiency in fiber bandwidth utilization is quite important for satisfying(More)
  • 1