Tomotaka Tabuchi

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A common requirement for all current and future TSV (Through Silicon Via) applications is the ability to handle and process thinned Silicon Wafers, usually in the range of 150μm or much below. Silicon Wafers of this thickness cannot be handled without support as wafers with the standard thickness. One solution to tackle this problem is the use of(More)
The development of 3D-SIC technology has been requiring more delicate backside processing with increasing complexity and process requirements. As one of the key enabling process steps, wafer backside thinning must also evolve to satisfy the emerging demands. In addition to extreme wafer thickness control, the process requirements has also been extended into(More)
We present a “carrierless” design for the manufacturing of ultrathin Silicon wafers, which are used in e.g. TSV (Through Silicon Via) and power chip applications. A carrierless wafer is a wafer which has a thinned inner portion, usually thinner than 150 μm, and a rim portion, which is stabilizing the wafer, so that the whole wafer can(More)
This paper presents a new carrierless approach to handling and processing ultra-thin Silicon which is predominantly used in processing Through Silicon Via (TSV) wafers. Currently, the state of the art consists of bonding the wafers having the vias onto a carrier wafer, after which the thinning steps of the wafer and the backside processing, e.g.(More)
Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified the suitable process flows. Within the process flow, laser grooving before plasma dicing was shown to be a key unit process to control resulting die sidewall quality.(More)
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