Tomonori Sekiguchi

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Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-<i>V<sub>T</sub></i> sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an(More)
A concordant memory-array design incorporates device fluctuation statistically into the signal-to-noise ratio analysis in DRAM and represents the failed bits in a chip. The proposed technique gives us a quantitative evaluation of the memory array and assures the operation of the 1.4 V array of a 100 nm - 1 Gb DRAM. The calculated dependence of failed bit(More)