Tomonori Sekiguchi

Learn More
Three DRAM technologies, which are a leakage- and soft-error-free planar-capacitor SOI cell, a data-line shielded twin (2-T) cell array, and an offset-free dynamic-<i>V<sub>T</sub></i> sense amplifier suitable for low-voltage mid-point sensing, are presented and evaluated. New noise-generation mechanisms are also shown. Using the experimental data of an(More)
A 5 GHz MIMO direct-conversion transceiver composed of 2 transmitters (TXs) and 3 receivers (RXs) is fabricated with 0.13 mum CMOS technology. Die size is 4.56 mm times 7.7 mm. For driving 10 GHz LO signal lines of 5 mm length for both TXs and RXs, inductor-less low-power LO repeaters are equipped in individual LO paths. A linearized RF variable gain(More)