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The constantly increasing complexity of today's systems demands specifications on highest levels of abstraction. In addition to a transition towards the system-level more elaborate techniques are necessary to close a growing productivity gap. Our solution to this problem is the application of the object-oriented programming paradigm together with the <i>de(More)
This contribution presents an approach, based on the usage of the object oriented programming language Java. The paper concentrates on the definition of an appropriate object model. The model differs considerably from other approaches with regard to its descriptive power. Normally, they are limited only to behavioral descriptions on the algorithmic level.(More)
This paper introduces an FPGA-based fault injection system. To realize this system a library was developed, which implements a static mapping between a circuit described at RTL or gate-level and its corresponding placed and routed FPGA design. The aim of this mapping is to preserve module and port structure of the placed and routed FPGA design to the(More)
We describe two things. First, we present a uniform framework for object oriented specification and verification of hardware. For this purpose the object oriented language &#8220;e&#8221; is introduced along with a powerful run-time environment that enables the designer to perform the verification task. Second, we present an object oriented synthesis that(More)
Hardware redundancy is a common method for improving the reliability of a system. The disadvantage of this approach is the hardware overhead and the additional power consumption. This contribution proposes a strategy for implementing low-cost triple modular redundancy (TMR) on coarse-grained reconfigurable architectures (CGRAs). Low-cost TMR is achieved by(More)
Object-oriented descriptions are gaining more and more importance in the high-level specification of hardware/software systems. Hiding the complexity from the developer is one of the key tasks in order to master the complexity of todays systems. With the high grade of abstraction necessary on the system level the automatic partitioning of a system is a(More)
Triple modular redundancy (TMR) is a common method to implement fault-tolerant circuits. Traditionally, TMR is realized by triplication of components. In order to reduce the area overhead of TMR another approach was proposed on coarse grained reconfigurable architectures (CGRAs). In that approach spare functional units (FUs) are used for redundant(More)