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—We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The trans-ceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on(More)
We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive(More)
This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM)(More)
This paper proposes and describes a new software and application programming interface view of an RF transceiver as implemented in the first single-chip GSM radio in 90 nm CMOS. It demonstrates benefits of using programmable digital control logic in deep-submicron CMOS RF system. It also describes a micro-processor architecture design in digital RF(More)
The first receiver system-on-chip (SoC) for the newly enhanced phase-modulation based WWVB broadcast is presented. Having an extensively digital architecture, and relying on the new features of the broadcast, it demonstrates 2-3 orders of receiver sensitivity superiority when compared to receiver ICs designed for the legacy WWVB broadcast. To allow for(More)
In this paper we present a quad-band single-chip GSM/GPRS radio in 90nm digital CMOS process based on the Digital RF Processor (DRP™) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging(More)