Tom Grutkowski

Learn More
July 2011 Revision 1.1 Poulson High Level Summary The next generation in the Intel® Itanium® processor family, code named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium® Processor 9300 series (Tukwila) [1]. The new design integrates a ring based system interface derived from portions of previous(More)
The next generation in the Itanium/spl reg/ processor family, code named Montecito is introduced. The processor has two dual-threaded cores integrated on die with 26.5MB of cache in a 90nm process with 7 layers of copper interconnect. The die is 21.5mm by 27.7mm and includes 1.72 billion transistors. With both cores at full frequency it consumes 100W. The(More)
Despite rumours of their demise, domino circuits are still indispensable in the design of high speed CMOS chips because they offer a 1.5-2x performance advantage over static logic. This tutorial briefly reviews basic dominio design issues, then compares and contrasts a wide variety of high-performance domino and nonmonotonic dynamic sequencing techniques.(More)
The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation. The most obvious being the incorporation of two legacy cores on-die and at the same time reducing power by 23%. This is an effective 325% increase in MIPS per watt which necessitated a holistic focus on power reduction and management.(More)
  • 1