Tom Grutkowski

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An Itanium® processor implemented in 32 nm CMOS with 9 layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has 8 multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of(More)
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