Tom Grutkowski

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An Itanium® processor implemented in 32 nm CMOS with 9 layers of Cu contains 3.1 billion transistors. The die measures 18.2 mm by 29.9 mm. The processor has 8 multi-threaded cores, a ring based system interface and combined cache on the die is 50 MB. High speed links allow for peak processor-to-processor bandwidth of up to 128 GB/s and memory bandwidth of(More)
The next generation in the Itanium/spl reg/ processor family, code named Montecito is introduced. The processor has two dual-threaded cores integrated on die with 26.5MB of cache in a 90nm process with 7 layers of copper interconnect. The die is 21.5mm by 27.7mm and includes 1.72 billion transistors. With both cores at full frequency it consumes 100W. The(More)
ISSP (Instant Solution Silicon Platform), the leading Structured ASIC Technology, was of great interest when introduced by NEC Electronics at DATE 2003. Now this tutorial will give you all the essential information required to judge the competitive advantage that using Structured ASIC can give you in your next project. ISSP devices are mask-programmed to(More)
—The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation. The most obvious being the incorporation of two legacy cores on-die and at the same time reducing power by 23%. This is an effective 325% increase in MIPS per watt which necessitated a holistic focus on power reduction and management.(More)
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