Tom Buggy

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Adapting software applications to embedded Multiprocessor System on Chips (MPSoCs) typically follows multithreaded design flows. To take advantage of the hardware customisations possible with MPSoCs, HardWare Threads (HWTs) can be used to increase application concurrency and throughput by forking between software and hardware execution. This paper describes(More)
Here we present our multi-core architectures for object detection. We move away from the traditional architecture of Multi-Processors (MPs) by using cacheable accesses to main memory to create atomic cores and utilising local memory for all program data. Main memory is partitioned through software into dedicated data regions to allow atomic accesses by(More)
This paper presents a novel Multiresolution, Perceptual and Vector Quantization (MPVQ) based video coding scheme. In the intra-frame mode of operation, a wavelet transform is applied to the input frame and decorrelates it into its frequency subbands. The coefficients in each detail subband are pixel quantized using a uniform quantization factor divided by(More)
In Mobile Ad-hoc Networks (MANETs), the majority of protocols developed to date provide QoS mechanisms by assigning high priority to delay-sensitive applications. While today's Internet traffic is still dominated by TCP based applications, the negative effects of the IEEE 802.11e service differentiation scheme on TCP performance in the presence of high(More)
This paper presents a novel architecture Soph.I.A (Sophisticated Intelligent Architecture), which integrates Knowledge Management and Data Mining into a unified Knowledge Discovery Process. Within SophIA Data Mining is driven by knowledge captured from domain experts. Knowledge Grid is briefly reviewed to envision the implementation of the proposed(More)
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